`timescale 1ns / 1ps

////////////////////////////////////////////////////////////////////////////////
// Company: 
// Engineer:
//
// Create Date:   21:04:20 05/22/2012
// Design Name:   QuadSpiTransceiver
// Module Name:   /home/azonenberg/native/programming/achd-soc/trunk/hdl/achd-soc/testQuadSpiTransceiver.v
// Project Name:  achd-soc
// Target Device:  
// Tool versions:  
// Description: 
//
// Verilog Test Fixture created by ISE for module: QuadSpiTransceiver
//
// Dependencies:
// 
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
// 
////////////////////////////////////////////////////////////////////////////////

module testQuadSpiTransceiver;

	// Inputs
	reg clk = 0;
	reg clk_n = 1;
	reg tx_en_single = 0;
	reg tx_en_quad = 0;
	reg [7:0] tx_data = 0;
	reg rx_en_single = 0;
	reg rx_en_quad = 0;

	// Outputs
	wire busy;
	wire done;
	wire spi_sck;
	wire [7:0] rx_data;

	// Bidirs
	wire [3:0] spi_data;

	// Instantiate the Unit Under Test (UUT)
	QuadSpiTransceiver uut (
		.clk(clk), 
		.busy(busy), 
		.done(done), 
		.spi_sck(spi_sck), 
		.spi_data(spi_data), 
		.tx_en_single(tx_en_single), 
		.tx_en_quad(tx_en_quad), 
		.tx_data(tx_data), 
		.rx_en_single(rx_en_single), 
		.rx_en_quad(rx_en_quad), 
		.rx_data(rx_data)
	);
	
	reg ready = 0;
	initial begin
		#100;
		ready = 1;
	end
	
	//Clock
	always begin
		clk = ready;
		clk_n = !ready;
		#6.25;
		clk = 0;
		clk_n = 1;
		#6.25;
	end
	
	//Test driver code
	reg[15:0] state = 0;
	always @(posedge clk) begin
		
		tx_en_single <= 0;
		tx_en_quad <= 0;
		tx_data <= 0;
		rx_en_single <= 0;
		rx_en_quad <= 0;
			
		case(state)
		
			//Send a byte in single mode
			0: begin
				tx_en_single <= 1;
				tx_data <= 8'hFF;
				state <= 1;
			end
			
			//Send another byte in single mode
			1: begin
				if(done) begin
					tx_en_single <= 1;
					tx_data <= 8'h55;
					state <= 2;
				end
			end
			
			//TODO
			2: begin
				
			end
			
			
		endcase
		
	end
      
endmodule

